1. Field of the Invention
The present invention relates to stroke writing cathode ray tube (CRT) displays particularly with respect to the vector generator therefor.
2. Description of the Prior Art
A variety of vector generator arrangements for stroke writing displays are known in the prior art. With such displays, images are formed by a composite of individually drawn vectors with concatenated vectors being utilized to compose display shapes and symbology. For present day applications, it is often desirable to display rotation of the images. A further desideratum of present day vector generators is precise control of vector writing speed whereby writing speeds may be fast enough for compatibility with present day processing rates and furthermore whereby smooth vectors may be written at a controlled slow speed. Slow vectors may be desirable to enhance display brightness without utilizing the conventional CRT brightness electronics. This is desirable since adjustment of the CRT brightness control often has a defocussing effect. The vector speed control may be utilized to adjust brightness on both shadow mask and penetration phosphor color CRTs as well as on other types of CRTs.
Analog vector generators utilizing analog ramp generators are known in the art. Such analog vector generators utilize an X ramp generator and a Y ramp generator to provide CRT deflection signals for generating the vectors. An X multiplier and a Y multiplier are utilized to rotate the images which results in a loss of precision. Such analog vector generators are generally incompatible with current digitally oriented systems and are imprecise, bulky and require significant amounts of power. The operating characteristics of the prior art analog vector generators drift with time and temperature thereby distorting the displayed images due to aging of the components.
Digital stroke vector generators are also known in the prior art. One type of digital vector generator prevalent in the art utilizes X and Y binary rate multipliers in the X and Y deflection axes respectively. The parallel digital multiplier inputs to the binary rate multipliers comprise the sine and cosine respectively of the angle of the vector to be drawn. The system clock signal applied to each of the binary rate multipliers is multiplied by the sine and cosine thereby providing X and Y clock pulse trains having pulse rates proportional to the sine and cosine. The X and Y clock pulses are counted in respective binary counters, the outputs of which provide digital X and Y position signals to respective X and Y digital-to-analog converters (DACs). The outputs of the X and Y DACs provide the X and Y deflection signals to the CRT.
State of the art DACs that are conventionally utilized in digital vector generators typically are twelve bits wide. Accordingly, in a rate multiplier vector generator utilizing twelve bit DACs, the sine and cosine rate inputs, the rate multipliers and the counters are also twelve bits wide. Thus, present day DACs providing twelve bit resolution can resolve to one part in 4,096. Such DACs have a settling time when changing from one value to another of approximately 300 nanoseconds. Therefore, when operating at maximum capability, the vector generator can traverse the full scale of the DAC range in approximately 1200 microseconds. Under such an arrangement, the input clock to the rate multipliers is 3.3 megahertz. This vector speed is an order of magnitude slower than typically required for CRT displays. If fewer bits are utilized, then vector speed may be increased with a concomitant and undesirable loss in resolution. Rate multiplier vector generators may additionally increase speed by utilizing a higher frequency clock input to the rate multipliers. Present day rate multipliers will accept frequencies up to thirteen megahertz. With such a clock input, the speed may be increased by a factor of 4 and if one bit is omitted from the DACs, an eight fold increase in speed can be achieved. It is appreciated in such an arrangement that because of the limited settling time of the DACs, the DACs are updated at a rate of approximately 3.3 megahertz.
The rate multiplier vector generator does not provide the resolution in X and Y deflection or the vector velocity control that is required in high performance CRT displays. Because of the inherent operation of rate multipliers, the beam does not move continuously in the X and Y directions and in fact the vector stops for a portion of time generally equal to (1-X rate) X (1-Y rate). This effect results in vectors having a granular appearance and the effect is exacerbated for low velocity vectors. With a rate multiplier vector generator, the velocity is reduced by reducing the sine and cosine rate inputs to the multipliers. This increases the proportion of clock cycles at which the rate multipliers do not produce any clock output. Thus, the velocity control is achieved by stopping the beam deflection more often and for longer durations for low velocity vectors. Instead, therefore, of generating a smooth slow vector, bright dots along the desired path result.
The resolution of rate multipliers cannot be improved further beyond that described above because the required frequency of the clock driving the rate multipliers would necessarily be higher than that accepted by present day rate multipliers. Thus, when complex display images which are composed of concatenated vectors is rotated or its perspective altered, errors of the individual vectors will accumulate to degrade the quality of the image. Increasing the length of the counters would not alleviate the problem since the rate multipliers cannot be driven fast enough to provide the required resolution. Displayed vectors are rotated by recomputing the sequence of sines and cosines for the incremental rotations of the vectors. With the limited accuracy and resolution of the rate multiplier vector generator as described above, the truncation errors of the arithmetic utilized in generating the sine and cosine values accumulate resulting in distortions of the rotating image.
A further prior art vector generator is disclosed in U.S. Pat. No. 4,115,863 issued Sep. 19, 1978 to Richard R. Brown entitled "Digital Stroke Display with Vector, Circle and Character Generation Capability" and assigned to the present assignee. The vector generator of said U.S. Pat. No. 4,115,863 generates vectors by applying clock pulses to an up/down counter which through a DAC provides the deflection voltage for one of the display X or Y axes. The clock pulses are applied through a gate to a second up/down counter which through a second DAC provides the deflection voltage for the other of the X and Y axes. The gate is controlled by the overflow of an accumulator that is repetitively accumulating, under control of the clock pulses, a signal representative of the desired slope of the vector. The DAC utilized in the display axis associated with the gated clock derives its input from both the associated up/down counter and the output of the associated accumulator for display resolution enhancement.
It is appreciated that in the vector generator of said U.S. Pat. No. 4,115,863, the display axis receiving the ungated clock has limited accuracy and resolution. Thus, when rotating display images comprised of concatenated vectors severe distortions occur for reasons similar to those discussed above. In addition, the vector generator of said U.S. Pat. No. 4,115,863 does not provide satisfactory vector velocity control and, therefore, the display brightness cannot be controlled as a function of vector writing speed. In such systems, display brightness must be controlled by the brightness circuitry of the apparatus which generally results in an undesirable alteration in focus with a change in brightness. The vector generator of said U.S. Pat. No. 4,115,863 suffers from non-uniform vector speed as a function of vector angle. It is desirable in such display systems to have as uniform a vector speed as possible for all vector angles. The vector generator of said U.S. Pat. No. 4,115,863 utilizes a complex octant switching arrangement to achieve proper vector orientation in the four display quadrants.